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This document presents the steps to setup an environment for using the EVAL-AD9838SDZ evaluation board together with the Xilinx KC705 FPGA board and the Xilinx Embedded Development Kit (EDK). Below is presented a picture of the EVAL-AD9838SDZ Evaluation Board with the Xilinx KC705 board.
For component evaluation and performance purposes, as opposed to quick prototyping, the user is directed to use the part evaluation setup. This consists of:
The SDP-B controller board is part of Analog Devices System Demonstration Platform (SDP). It provides a high speed USB 2.0 connection from the PC to the component evaluation board. The PC runs the evaluation software. Each evaluation board, which is an SDP compatible daughter board, includes the necessary installation file required for performance testing.
Note: it is expected that the analog performance on the two platforms may differ.
Below is presented a picture of SDP-B Controller Board with the EVAL-AD9838SDZ Evaluation Board.
The AD9838 is a 16 MHz low power DDS device capable of producing high performance sine and triangular outputs. It also has an on-board comparator that allows a square wave to be produced for clock generation. Consuming only 11 mW of power at 2.3 V makes the AD9838 an ideal candidate for power-sensitive applications.
The EVAL-AD9838SDZ evaluation board is designed to help customers quickly prototype new AD9838 circuits and reduce design time. A high performance, on-board 16 MHz trimmed general oscillator is available to use as the master clock for the AD9838 system. Various links and SMB connectors are also available on the EVAL-AD9838SDZ board to maximize usability.
The first objective is to ensure that you have all of the items needed and to install the software tools so that you are ready to create and run the evaluation project.
Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page.
The following commands were implemented in this version of EVAL-AD9838 reference project for Xilinx KC705 FPGA board.
| Command | Description |
|---|---|
| help? | Displays all available commands. |
| output= | Selects the type of output. Accepted values: 0 - Sinusoid.(default) 1 - Triangle. |
| output? | Displays the type of output. |
| loadFreqReg= | Loads a frequency value in one selected register. Accepted values: Register number: 0 - Frequency Register 0. 1 - Frequency Register 1. Value: 0 .. 8 000 000 - the frequency value in Hz. |
| freqRegVal? | Displays the value from one selected frequency register. Accepted values: Register number: 0 - Frequency Register 0. 1 - Frequency Register 1. |
| loadPhaseReg= | Loads a phase value in one selected register. Accepted values: Register number: 0 - Phase Register 0. 1 - Phase Register 1. Value: 0 .. 2PI - the phase value in radians. |
| phaseRegVal? | Displays the value from one selected phase register. Accepted values: Register number: 0 - Phase Register 0. 1 - Phase Register 1. |
| freqRegNo= | Select the frequency register to be used. Accepted values: Register number: 0 - Frequency Register 0. 1 - Frequency Register 1. |
| freqRegNo? | Displays the selected frequency register. |
| phaseRegNo= | Select the phase register to be used. Accepted values: Register number: 0 - Phase Register 0. 1 - Phase Register 1. |
| phaseRegNo? | Displays the selected phase register. |
| sleepMode= | Select one sleep mode. Accepted values: Sleep mode: Soft method: 0 - No power-down.(default) 1 - DAC powered down. 2 - Internal clock disabled. 3 - DAC powered down and Internal clock disabled. Hard method: 0 - No power-down.(default) 1 - DAC powered down. |
| sleepMode? | Displays the selected sleep mode. |
| program= | Sets the programming method. Accepted values: Method: 0 - Soft programming method.(default) 1 - Hard programming method. |
| program? | Displays the programming method. |
| logicOut= | Sets the logic output type. Accepted values: Logic output type: 0 - High impedance.(default) 1 - DAC data MSB/2. 2 - DAC data MSB. 3 - Comparator. |
| logicOut? | Displays the logic output type. |
Commands can be executed using a serial terminal connected to the UART peripheral of Xilinx KC705 FPGA.
The following image shows a generic list of commands in a serial terminal connected to Xilinx KC705 FPGA's UART peripheral.
The hardware platform for each reference projects with FMC-SDP interposer and KC705 evaluation board is common. The next steps should be followed to recreate the software project of the reference design:
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