分享资料个
The AD9528 is a two-stage PLL with an integrated JESD204B SYSREF generator for multiple device synchronization. The first stage phase-locked loop （PLL） （PLL1） provides input reference conditioning by reducing the jitter present on a system clock. The second stage PLL （PLL2） provides high frequency clocks that achieve low integrated jitter as well as low broadband noise from the clock output drivers. The external VCXO provides the low noise reference required by PLL2 to achieve the restrictive phase noise and jitter requirements necessary to achieve acceptable performance. The on-chip VCO tunes from 3.450 GHz to 4.025 GHz. The integrated SYSREF generator outputs single shot， N-shot， or continuous signals synchronous to the PLL1 and PLL2 outputs to time align multiple devices. The AD9528 generates two outputs （Output 1 and Output 2） with a maximum frequency of 1.25 GHz， and 12 outputs up to 1 GHz. Each output can be configured to output directly from PLL1， PLL2， or the internal SYSREF generator. Each of the 14 output channels contains a divider with coarse digital phase adjustment and an analog fine phase delay block that allows complete flexibility in timing alignment across all 14 outputs. The AD9528 can also be used as a dual input flexible buffer to distribute 14 device clock and/or SYSREF signals. At power-up， the AD9528 sends the VCXO signal directly to Output 12 and Output 13 to serve as the power-up ready clocks. Note that， throughout this data sheet， the dual function pin names are referenced by the relevant function where applicable.
声明：本文内容及配图由入驻作者撰写或者入驻合作网站授权转载。文章观点仅代表作者本人，不代表电子发烧友网立场。文章及其配图仅供工程师学习之用，如有内容侵权或者其他违规问题，请联系本站处理。 举报投诉
dozo_shen
2019-01-29
全部1条评论
快来发表一下你的评论吧 !
