The AD9250 is a dual, 14-bit ADC with sampling speeds of up to 250 MSPS. It is designed to support communications applications where low cost, small size, wide bandwidth and versatility are desired. The ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. This reference design includes the device data capture via the JESD204B serial interface and the SPI interface. The samples are written to the external DDR-DRAM on the carrier. It allows programming the device and monitoring its internal registers via SPI.

A native FMC card with the AD9250 can be found FMCJESDADC1 Board

• AD9250 Evaluation Board
• ADC FMC Interposer Board

• KC705
• VC707
• ZC706

The reference design zip file contains a bit file and a SDK elf file for a quick demonstration of the programming and data capture. The reference design has been tested with KC705, VC707 and ZC706. The notes below refer to KC705, the procedure is same for the other boards. Please make sure you are using the correct reference design for the board(s) that you have.

• KC705/VC707/ZC706 board
• AD9250-EBZ board & Power supply (AD9250-250EBZ, AD9250-170EBZ)
• ADC FMC interposer board (CVT-ADC-FMC-INTPZB)
• Signal/Clock generator (reference clock input, 250MHz)
• Signal generator (analog input, for data capture)

• Xilinx ISE Design Suite 14.4
• A UART terminal (Tera Term/Hyperterminal), Baud rate 57600 (115200 for ZC706).

The reference design contains UCF files for the Rev. B board, CVT-ADC-FMC-INTPZB.

• NET rxdata_p[1] LOC = “B6”;
• NET rxdata_n[1] LOC = “B5”;
• NET rxdata_p[0] LOC = “D6”;
• NET rxdata_n[0] LOC = “D5”;
• NET rxsync_p LOC = “C29” | IOSTANDARD = “LVDS_25”;
• NET rxsync_n LOC = “B29” | IOSTANDARD = “LVDS_25”;
• NET rxsysref_p LOC = “D29” | IOSTANDARD = “LVDS_25”;
• NET rxsysref_n LOC = “C30” | IOSTANDARD = “LVDS_25”;

• NET spi_ctrl LOC = “K13” | IOSTANDARD = “LVCMOS25”;
• NET spi_csn[0] LOC = “B18” | IOSTANDARD = “LVCMOS25”;
• NET spi_csn[1] LOC = “A18” | IOSTANDARD = “LVCMOS25”;
• NET spi_clk LOC = “G17” | IOSTANDARD = “LVCMOS25”;
• NET spi_mosi LOC = “A17” | IOSTANDARD = “LVCMOS25”;
• NET spi_miso LOC = “A16” | IOSTANDARD = “LVCMOS25”;

Please do the following modifications on the AD9250 evaluation board.

• Remove R609
• Remove R610
• Remove R604
• Remove R601
• Remove R551*
• Remove R552*
• Populate R549*
• Populate R550*

* The reference design uses REFCLK2 as the reference clock source. If the board defaults to REFCLK1, follow these instructions to switch to REFCLK2.

To begin make the following connections (see image below):

1. Connect the AD9250-EBZ board to the FMC Interposer board.
2. Connect the interposer board to the FMC-HPC connector of KC705/(FMC1-HPC if VC707)/ZC706 board.
3. Connect power to KC705/VC707/ZC706 and the AD9250-EBZ boards. Make sure both are turned on.
4. Connect two USB cables from the PC to the JTAG and UART USB connectors on KC705/VC707/ZC706. Do not run/load any software yet.
5. Connect an external clock source 250MHz (5dBm) to AD9250-EBZ board's J505 SMA connector. Make sure this is active/on.
6. Connect signal generators to the AIN-A and/or AIN-B, J301/J303 SMA connectors.
7. Load the FPGA image/SDK with your favorite Xilinx Tool.

The quick start bit file configures the AD9250 for all test modes and verifies the captured data accordingly. After the hardware setup, turn the power on to the KC705/VC707/ZC706 and the AD9250-EBZ boards.

Run the download.bat script located in the “SDK/SDK_Workspace/bin” folder provided within the HDL Reference Design. This script uses XMD to program the FPGA with the HDL Reference Design and download the Software Reference Design into the DDR.

Note: The download.bat script assumes that the Xilinx ISE Design Suite 14.4 is installed at this path: C:/Xilinx/14.4. If the installation path on your computer is different please modify the script accordingly.

If programming was successful, you should be seeing messages appear on the terminal as shown in figure below. After programming the AD9250, the program checks data capture on various test modes.

After the ADC test patterns and PRBS sequences are verified, if no errors are present, the reference design continuously reads data from the ADC. The ADC data can be viewed using the Chipscope project located in the “Chipscope” folder provided in the HDL Reference Design. These are the steps than need to be followed to view the ADC data in Chipscope:

• open Chipscope and press the Open Cable/Search JTAG Chain button (the leftmost button located under the File menu)
• open the Chipscope/AD9250.cpj project
• start the data capture

This is how the output of the ADC looks like.

The reference design is built on a microblaze based system parameterized for linux. A functional block diagram of the design is given below.

The reference design consists of two pcores. The JESD204B core consists of the GTX units and the Xilinx JESD204B IP core. The AD9250 core consists of three functional modules, the ADC interface, a PN9/PN23 monitor and a DMA interface.

The ADC interface captures and buffers data from the JESD204B core. The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software. The status of capture (overflow, overrange) are reported back to the software.

The JESD204B core and AD9250 core has an AXI lite interface that allows control and monitoring of the capture process.

The reference design also includes the HDMI cores to run GTX eye scan.

Please refer to the regmap.txt file in the pcores directory.

The PN9/PN23 sequences are not compatible with O.150. Please use the equations given in the reference design.

The Software Reference Design contains an example on how to:

• Initialize the AD9250 evaluation board
• Initialize the JESD204B HDL core
• Test the ADC communication using the test patterns and PRBS sequences generated by the AD9250
• Capture data from the AD9250 using DMA transfers

The software project contains 2 components: the AD9250-EBZ reference design files and the AD9250 driver. All the components have to be downloaded from the links provided in the Downloads section.

Below is presented a short description of all the functions provided in the driver.

The HDL Reference Design for each supported Xilinx FPGA board contains a folder called SDK_Workspace which stores the Xilinx SDK project files needed to build the no-OS software and also the .bit files with the HDL design that must be programmed into the FPGA. These are the steps that need to be followed to recreate the software project:

• Copy the SDK_Workspace folder on your PC. Make sure that the path where it is stored does not contain any spaces.
• Copy the no-OS drivers source code to the SDK_Workspace/sw/src folder.

• Open the Xilinx SDK. When the SDK starts it asks you to provide a folder where to store the workspace. Any folder can be provided.
• In the SDK select the File→Import menu option to import the software projects into the workspace.

• In the Import window select the General→Existing Projects into Workspace option.

• In the Import Projects window select the SDK_Workspace folder as root directory. After the root directory is chosen the projects that reside in that directory will appear in the Projects list. Press Finish to finalize the import process.

• The Project Explorer window now shows the projects that exist in the workspace and the files for each project. The SDK should automatically build the projects and the Console window will display the result of the build. If the build is not done automatically select the Project→Build Automatically menu option.

• At this point the software project setup is complete, the FPGA can be programmed and the software can be downloaded into the system.

The example code is located in the ”main.c” file and the implementations of the test routines can be found in the “cf_ad9250.c” file.

The HDL Reference Designs and the no-OS Software can be downloaded from the Analog Devices github.

HDL Reference Designs:

no-OS Software:

Board Files: